diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 2ba03ed..508ebfb 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -551,43 +551,6 @@
 		eeprom->use_eerd = true;
 		eeprom->use_eewr = false;
 		break;
-
-	/* ich8lan does not support currently. if needed, please
-	 * add corresponding code and functions.
-	 */
-#if 0
-	case e1000_ich8lan:
-		{
-		int32_t  i = 0;
-
-		eeprom->type = e1000_eeprom_ich8;
-		eeprom->use_eerd = false;
-		eeprom->use_eewr = false;
-		eeprom->word_size = E1000_SHADOW_RAM_WORDS;
-		uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
-				ICH_FLASH_GFPREG);
-		/* Zero the shadow RAM structure. But don't load it from NVM
-		 * so as to save time for driver init */
-		if (hw->eeprom_shadow_ram != NULL) {
-			for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
-				hw->eeprom_shadow_ram[i].modified = false;
-				hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
-			}
-		}
-
-		hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
-				ICH_FLASH_SECTOR_SIZE;
-
-		hw->flash_bank_size = ((flash_size >> 16)
-				& ICH_GFPREG_BASE_MASK) + 1;
-		hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
-
-		hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
-
-		hw->flash_bank_size /= 2 * sizeof(uint16_t);
-		break;
-		}
-#endif
 	default:
 		break;
 	}
@@ -838,14 +801,6 @@
 	if (eeprom->use_eerd == true)
 		return e1000_read_eeprom_eerd(hw, offset, words, data);
 
-	/* ich8lan does not support currently. if needed, please
-	 * add corresponding code and functions.
-	 */
-#if 0
-	/* ICH EEPROM access is done via the ICH flash controller */
-	if (eeprom->type == e1000_eeprom_ich8)
-		return e1000_read_eeprom_ich8(hw, offset, words, data);
-#endif
 	/* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 	 * acquired the EEPROM at this point, so any returns should relase it */
 	if (eeprom->type == e1000_eeprom_spi) {
@@ -1732,17 +1687,7 @@
 		 * occuring when accessing our register space */
 		E1000_WRITE_FLUSH(hw);
 	}
-#if 0
-	/* Set the PCI priority bit correctly in the CTRL register.  This
-	 * determines if the adapter gives priority to receives, or if it
-	 * gives equal priority to transmits and receives.  Valid only on
-	 * 82542 and 82543 silicon.
-	 */
-	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
-		ctrl = E1000_READ_REG(hw, CTRL);
-		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
-	}
-#endif
+
 	switch (hw->mac_type) {
 	case e1000_82545_rev_3:
 	case e1000_82546_rev_3:
@@ -1842,20 +1787,6 @@
 		break;
 	}
 
-#if 0
-	/* Clear all of the statistics registers (clear on read).  It is
-	 * important that we do this after we have tried to establish link
-	 * because the symbol error count will increment wildly if there
-	 * is no link.
-	 */
-	e1000_clear_hw_cntrs(hw);
-
-	/* ICH8 No-snoop bits are opposite polarity.
-	 * Set to snoop by default after reset. */
-	if (hw->mac_type == e1000_ich8lan)
-		e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
-#endif
-
 	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
 		hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
 		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -5230,10 +5161,6 @@
 	E1000_WRITE_REG(hw, RDH, 0);
 	E1000_WRITE_REG(hw, RDT, 0);
 
-	/* put the card in its initial state */
-#if 0
-	E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
-#endif
 	mdelay(10);
 }
 
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index c851922..e46edcd 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -1093,11 +1093,6 @@
 	e1000_media_type media_type;
 	e1000_fc_type fc;
 	e1000_bus_type bus_type;
-#if 0
-	e1000_bus_speed bus_speed;
-	e1000_bus_width bus_width;
-	uint32_t io_base;
-#endif
 	uint32_t		asf_firmware_present;
 #ifndef CONFIG_E1000_NO_NVM
 	uint32_t		eeprom_semaphore_present;
@@ -1116,29 +1111,11 @@
 	uint32_t original_fc;
 	uint32_t txcw;
 	uint32_t autoneg_failed;
-#if 0
-	uint32_t max_frame_size;
-	uint32_t min_frame_size;
-	uint32_t mc_filter_type;
-	uint32_t num_mc_addrs;
-	uint32_t collision_delta;
-	uint32_t tx_packet_delta;
-	uint32_t ledctl_default;
-	uint32_t ledctl_mode1;
-	uint32_t ledctl_mode2;
-#endif
 	uint16_t autoneg_advertised;
 	uint16_t pci_cmd_word;
 	uint16_t fc_high_water;
 	uint16_t fc_low_water;
 	uint16_t fc_pause_time;
-#if 0
-	uint16_t current_ifs_val;
-	uint16_t ifs_min_val;
-	uint16_t ifs_max_val;
-	uint16_t ifs_step_size;
-	uint16_t ifs_ratio;
-#endif
 	uint16_t device_id;
 	uint16_t vendor_id;
 	uint16_t subsystem_id;
@@ -1149,9 +1126,6 @@
 	uint8_t forced_speed_duplex;
 	uint8_t wait_autoneg_complete;
 	uint8_t dma_fairness;
-#if 0
-	uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
-#endif
 	bool disable_polarity_correction;
 	bool		speed_downgraded;
 	bool get_link_status;
@@ -1162,11 +1136,6 @@
 	bool report_tx_early;
 	bool phy_reset_disable;
 	bool		initialize_hw_bits_disable;
-#if 0
-	bool adaptive_ifs;
-	bool ifs_params_forced;
-	bool in_ifs_mode;
-#endif
 	e1000_smart_speed	smart_speed;
 	e1000_dsp_config	dsp_config_state;
 };